1. Field of the Invention
This invention relates to a two-dimensional solid-state image pickup device of a gate accumulation system using static induction transistors.
2. Description of the Prior Art
Regarding the formation and signal detecting method of a conventional solid-state image pickup device by a gate accumulation system using static induction transistors (which shall be called SIT's hereinafter), various systems have been already suggested by the present inventors and are disclosed in Japanese patent applications Nos. 204656/1981, 217758/1982, 21688/1983 and 26932/1983. Further, the experiment results are published in "SIT Image Converter" by J. Nishizawa, T. Tamamushi and S. Suzuki in JARECT (Japan Annual Review in Electronics, Computers and Telecommunications) in Semiconductor Technologies Vol. 8 (October 1983) edited by J. Nishizawa (OHM & North Holland).
Further, a reading system utilizing a capacitor of a signal reading line in an X-Y address system as different from the formation and signal reading method of the conventional SIT image sensor have been already suggested by the present inventors and are discosed in Japanese patent application No. 208116/1983. Its formation and signal reading system shall be explained in the following with reference to FIGS. 1A to 2B.
In FIG. 1A, one picture elements C.sub.ij is formed of a normally off SIT and gate capacitor C.sub.G, an address gate line GL.sub.j is connected to a gate 31 of the SIT through the gate capacitor C.sub.G and a signal reading line SL.sub.i is connected to a drain 30. Further, two switching transistors Q.sub.P and Q.sub.S are connected to the signal reading line SL.sub.i, a video bias voltage V.sub.DD is impressed onto a drain terminal (output terminal) 10 of the switching transistor Q.sub.S through a load resistance R.sub.L and a constant bias voltage V.sub.DD ' is impressed also onto a drain terminal 20 of the switching transistor Q.sub.P. Here, the parasitic capacitance of the signal reading line SL.sub.i is indicated by C.sub.SL. The information of the picture element C.sub.ij, by a light input h.nu. is accumulated in the gate of the SIT. Then, the reading operation shall be explained. As shown in FIG. 1B, in the case of reading out the light information of the picture element C.sub.ij, first the switching transistor Q.sub.P is made conductive by precharging pulses .phi..sub.P to charge the line SL.sub.i with a predetermined voltage V.sub.DD '-V.sub.thp where V.sub.thp represents a threshold voltage of the switching transistor Q.sub.P. Then, when address gate pulses .phi..sub.Gj are impressed onto the address gate line GL.sub.j and gate pulses are impressed on the gate part 31 of the SIT through the gate capacitor C.sub.G of the picture element C.sub.ij to make the SIT conductive, the impedance between the drain 30 and source 32 of the SIT will lower and therefore the voltage V.sub.DD '-V.sub.thp with which the capacitor C.sub.SL has been charged will be discharged. At this time, the gate potential by a carrier as the light information accumulated in the gate 31 of the SIT will be raised by the address gate pulses .phi..sub.Gj added from outside and therefore the stronger the light intensity, the larger the discharge current following between the drain 30 and source 32 of the SIT.
If I.sub.L represents an incident light current and I.sub.S represents a reverse direction saturated current of a pin diode around the gate 31 of the SIT, a potential rise .DELTA.V.sub.G of the gate 31 of the SIT by a carrier generated by the light input h.nu. will be given substantially by the following formula where k represents Boltzmann's constant, T represents an absolute temperature and q represents a unit charge amount: ##EQU1##
On the other hand, the relation between the gate voltage V.sub.G and drain current I.sub.D of the normally off SIT is an exponential function and is represented by ##EQU2## where .eta. represents the rate of the gate voltage of SIT covering the intrinsic gate point.
On the other hand, in case the light intensity is weak, the light current I.sub.L by the light input h.mu. will be proportional to the incident intensity P (.mu.W/cm.sup.2). Therefore, in the above mentioned reading operation, the discharge current I.sub.DC flowing between the drain 30 and source 32 of the SIT is represented by ##EQU3##
In the case of the normally off SIT, .eta. may be .eta..apprxeq.1. Therefore, the discharge current I.sub.DC of the capacitor C.sub.SL charged with V.sub.DD '-V.sub.thp is found to be proportional to the light current I.sub.L or incident light intensity P (.mu.W/cm.sup.2).
In FIG. 1B, V.sub.SLi represents a voltage waveform at each end of the capacitor C.sub.SL or a voltage variation of the signal reading line SL.sub.i and varies as in the dotted line a, one-point chain line b or solid line c with the impression of the address gate pulse .phi..sub.Gj to be on a voltage level lower than the voltage represented by V.sub.DD '-V.sub.thp. The dotted line a corresponds to the case of a dark current state, the one-point chain line b corresponds to the case of an ordinary light intensity and the solid line c corresponds to the case of a saturated exposure state. This time constant of the discharge is determined substantially by the product of the on-resistance value R.sub.on(SIT) between the drain and source of the SIT and the capacitance of the capacitor C.sub.SL in the circuit in FIG. 1A. It is a desirable condition that, when a dark current is flowing, even if the address gate pulses .phi..sub.Gj are impressed as shown by the dotted line in FIG. 1B, the SIT will not be conductive, because, when a dark current is flowing, if the discharge of the capacitor C.sub.SL occurs with only the impression of the address gate pulses .phi..sub.Gj, a dark current signal will appear on the output waveform and the S/N of the ordinary light signal will deteriorate.
When the capacitor C.sub.SL is discharged by the impression of the address gate pulses .phi..sub.Gj as described above and is then recharged with the discharge amount, a recharge signal will appear at each end of the external resistance R.sub.L.
When the transistor Q.sub.S is made conductive by the impression of the reading address pulses .phi..sub.Si onto the gate of the switching transistor Q.sub.S, the capacitor C.sub.SL will be charged with a voltage value represented by V.sub.DD -V.sub.ths where V.sub.ths represents a threshold voltage of the switching transistor Q.sub.S. In this case, V.sub.DD -V.sub.ths is usually selected to be EQU V.sub.DD -V.sub.ths =V.sub.DD '-V.sub.thp ( 4).
In FIG. 1B, the waveform shown by V.sub.SLi shows how the capacitor C.sub.SL is recharged by the impression of the reading address pulses .phi..sub.Si. Simultaneously with this recharging, at each end of the load resistance R.sub.L, a signal represented by V.sub.out (enlarged waveform will be detected). The dotted line a corresponds to a dark current state, the one-point chain line b corresponds to the case of an ordinary light intensity and the solid line c corresponds to a saturated exposure state.
As evident from the above described explanation, in the conventional signal reading method, the parasitic capacitor C.sub.SL of the signal reading line SL.sub.i is utilized and the information of the inner picture element C.sub.ij is taken out at the load resistance R.sub.L after the process of charging-up the capacitor C.sub.SL by the precharging transistor Q.sub.P, the discharge proportional to the light information of the capacitor C.sub.SL by the address gate pulses .phi..sub.Gj and the recharge of the capacitor C.sub.SL through the switching transistor (transistor for selecting the signal reading line SL.sub.i) Q.sub.S. It is a feature in the sense of obtaining a stable and uniform signal that the gate pulses .phi..sub.Gj will be addressed when the line SL.sub.i is charged with a predetermined potential always in reading out through the switching transistor Q.sub.P and a constant voltage is set to be applied between the drain 30 and source 32 of the SIT. The discharge amount of the capacitor C.sub.SL can be very easily read out through the switching transistor Q.sub.S. In the case of the above described operation made with reference to FIGS. 1A and 1B, when the load resistance is represented by R.sub.L, the on-resistance of the switching transistor Q.sub.S is represented by R.sub.ONS and the parasitic capacitance of the signal reading line SL.sub.i is represented by C.sub.SL, the time constant of the output waveform V.sub.out at the output terminal 10 will be determined by (R.sub.L +R.sub.ONS).C.sub.SL.
Now, the formation example and operating waveform example of a conventional two-dimensional solid-state image pickup device based on the operation principle explained with reference to FIGS. 1A and 1B shall be explained with reference to FIGS. 2A and 2B.
Each of the picture elements C.sub.ij (C.sub.11, C.sub.12, . . . , C.sub.1m ; C.sub.21 , . . . C.sub.2mj . . . ) arranged in the form of a matrix of m.times.n is formed of an SIT and gate capacitor C.sub.G, the gates of the respective SIT's are connected to address gate lines GL.sub.1, GL.sub.2, GL.sub.3, . . . GL.sub.m respectively through the gate capacitors C.sub.G and the drains of the respective SIT's are connected respectively to signal reading lines SL.sub.1, SL.sub.2, SL.sub.3, . . . , SL.sub.n. The sources of the respective SIT's are of earthed potentials common to all the picture elements. Further, a precharging transistor Q.sub.P and two switching transistors Q.sub.T and Q.sub.S are connected on respective signal reading lines SL.sub.i, the gate line 54 of the precharging transistors Q.sub.P is made to be connected in common at the gates of the precharging transistors Q.sub.P on the respective signal reading lines SL.sub.i and the gate line 53 of the switching transistors Q.sub.T is also made to be connected in common at the gates of the respective switching transistor Q.sub.T on the respective signal reading lines SL.sub.i. Signal reading line selecting pulse trains .phi..sub.S1, .phi..sub.S2, .phi..sub.S3, . . . .phi..sub.Sm from a horizontal shift register 50 are so formed to be impressed onto the gates of the respective switching transistors Q.sub.S, the drain terminals of the respective switching transistors Q.sub.S are connected in common to a video output line 51 and one load resistance R.sub.L and video current source V.sub.DD are connected on this video output line 51. A signal output is obtained from each end of the load resistance R.sub.L. Address gate pulses .phi..sub.G1, .phi..sub.G2, .phi..sub.G3, . . . , .phi..sub.Gn are made to be impressed onto the respective address gate lines GL.sub.1, GL.sub.2, GL.sub.3, . . . , GL.sub.m from a vertical shift register 52. More particularly, the drain terminals of the respective precharging transistors Q.sub.P are connected in common to a current source line 55 to which a precharging voltage V.sub.DD, is given.
In FIG. 2A, the parasitic capacitors of the respective signal reading lines SL.sub.1, SL.sub.2, SL.sub.3, . . . , SL.sub.n are expressed as C.sub.SL, the capacitor between the gate and drain of the switching transistor Q.sub.T is expressed as C.sub.T and the capacitor which the drain of the switching transistor Q.sub.T and the source terminal of the switching transistor Q.sub.S have for the earthed potential is expressed as C.sub.SL '. In order to effectively take out the light information of each picture element onto the video line 51, the sizes of the respective capacitors are made as follows: EQU C.sub.G &lt;C.sub.SL '.apprxeq.C.sub.T .ltorsim.C.sub.SL ( 5)
Further, the values of the respective current source voltages are so selected that, if the threshold value voltage of each precharging transistor Q.sub.P is represented by V.sub.thp, the threshold voltages of switching transistors Q.sub.T and Q.sub.s are represented respectively by V.sub.tht and V.sub.ths, the height of the precharging pulse .phi..sub.P is represented by V.sub.DD ', the height of the transfer gate pulse .phi..sub.T is represented by V.sub.DD ' and the heights of the respective horizontal shift pulses .phi..sub.S1, .phi..sub.S2 , . . . , .phi..sub.Sm are assumed to equal to V.sub.DD, then EQU V.sub.DD '-V.sub.thp -V.sub.tht =V.sub.DD -V.sub.ths ( 6).
Reversely speaking, reading under stable and uniform conditions is made by selecting the height V.sub.DD ' of the transfer gate pulse .phi..sub.T, the height of the precharging pulse .phi..sub.P, the threshold value voltages V.sub.thp and V.sub.tht, the height of the transfer gate pulse .phi..sub.T, the threshold value voltage V.sub.ths and the height of the horizontal shift pulses .phi..sub.Si (i =1.about.n) so that the voltage level on which signal reading line SL.sub.i is precharged and the capacitor C.sub.SL ' is charged may be equal to the voltage level on which the capacitor C.sub.SL ' is recharged by the conduction of the switching transistor Q.sub.S. The source of the SIT's forming the respective picture elements is made common to all the picture elements by an n.sup.+ substrate or n.sup.+ embedded layer and further the SIT's forming the respective picture elements have the drains and gates separated from each other in the same semiconductor substrate so that the picture element signals may be separated from each other. Only the drains of the SIT's connected to the same signal reading line SL.sub.i are made electrically common.
FIG. 2B shows examples of reading operation waveforms of the conventional two-dimensional solid-state image pickup device shown in FIG. 2A. The operation waveforms shown in FIG. 2B show reading operation waveforms in the case that the light informations of the picture elements arranged in the form of a matrix of m.times.n are read out in turn as (C.sub.11, C.sub.21, C.sub.22, . . . , C.sub.n1), (C.sub.12, C.sub.22, C.sub.32, . . . , C.sub.n2), . . . (C.sub.1j, C.sub.2j, C.sub.3j, . . . , C.sub.nj), (C.sub.1j+1, C.sub.2j+1, C.sub.3j+1, . . . , C.sub.nj+1), . . . (C.sub.1m, C.sub.2m, . . . C.sub.nm). There is an improved type wherein the reading signal lines are scanned by skipping each line by applying an operating principle utilizing charging and discharging the parasitic capacitors C.sub.SL of the same signal reading line but the essential part is shown in FIG. 2B. Further, there is also a method of improving the operating waveforms in FIG. 2B. For example, there is a method wherein a function of adding onto the same gate address line GL.sub.j such pulses higher than the pulse height of the address gate pulses .phi..sub.Gj as, for example, refreshed pulses of more than 2.5 V and a pulse width within several .mu. sec. in a horizontal retracing period existing for only several .mu.sec. after one horizontal reading period is added to the respective address gate pulses .phi..sub.Gi. In the signal reading system shown in FIGS. 2A and 2B, as the address gate pulses .phi..sub.Gi are added, the light informations of the respective picture elements will move to the capacitors C.sub.SL and C.sub.SL ' within a short time within the pulse width (less than several .mu.sec.), the address gate pulses .phi..sub.Gi (of a height of 2 V and pulse width within several .mu.sec.) will be added at the time of the address gate and refreshed pulses (of more than 2.5 V and within several .mu.sec.) higher than the address gate pulses .phi..sub.Gi on the same line will be added in the horizontal retracing period substantially after the lapse of one horizontal period or just after the pulses of the transfer gate pulses .phi..sub.T are cut and the capacitors C.sub.SL and C.sub.SL ' are separated from each other. However, most simply, if address gate pulses of a pulse height of more than 2.5 V and pulse width within several .mu.sec. are used for the address gate pulses .phi..sub.Gj as shown in FIG. 2B, at the time of addressing the address gate pulses .phi..sub.Gj, substantially all the carriers accumulated in the gate will be refreshed and therefore it will be no longer necessary to add the refreshed gate pulses in the horizontal retracing period or just after the pulses of the transfer gate pulses .phi..sub.T are cut. The higher the pulse height of the gate, the larger the spike noise accompanying the switching. Therefore, in case the switching spike noise is a problem, the function of controlling the height of the address gate pulses .phi..sub.Gj to be within 2 V and adding refreshed pulses in one horizontal retracing period or just after the pulses of the transfer gate pulses .phi..sub.T are cut will become effective. Therefore, here the simplest operating waveform is shown in FIG. 2B.
The operation of the above mentioned device shall be explained on the basis of FIG. 2B. The difference of the formation in FIG. 2A from the formation in FIGS. 1A and 1B is that the switching transistors Q.sub.T are added on the signal reading lines SL.sub.i (i =1 .about.n). This is for the following reasons. The m SIT's are connected to the same signal reading lines SL.sub.i. In the light detecting state, the light will be irradiated to the respective SIT's, carriers will be accumulated in the gates, therefore the height of the potential barrier existing within the channel between the source and drain of each SIT will reduce and therefore the impedance between the signal reading line SL.sub.i and the ground will gradually reduce with the integrated amount of the light. When the impedance between the signal reading line SL.sub.i and the ground reduces, the potential with which the capacitor (C.sub.SL +C.sub.SL ') has been charged will be discharged. This discharged amount will correspond to the sum of light informations for one train. Of what picture element the light information will be unable to be specified. On the other hand, the light informations will be accumulated in the gate of each SIT and therefore will not be lost even if the potential of the signal reading line SL.sub.i fluctuates. The time after the horizontal shift pulses .phi..sub.Si are added until the horizontal shift pulses .phi..sub.Sn are added is substantially equal to one horizontal retracing period and is about 60 .mu.sec. in the TV signal. Therefore, with the formation shown in FIGS. 1A and 1B as it is, in the period after the signal reading line SL.sub.i (i =1 .about.n) is precharged by the precharging signal, the same signal line GL.sub.j is addressed and the first picture element C.sub.1j is read out by the horizontal shift pulses .phi..sub.S1 until the picture element C.sub.nj is read out by the horizontal shift pulses .phi..sub.Sn, the precharged voltage level will be easier to discharge in the later signal reading lines. Particularly, the precharged potential of the signal reading line SL.sub.n must be kept constant for about 60 .mu.sec. until the picture element C.sub.nj is read out by the horizontal shift pulses .phi..sub.Sn. Meanwhile, the influence of the light received by the other picture elements connected to the same signal reading line SL.sub.i must by controlled as much as possible. However, as evident from experiments, the more the picture elements arranged on one horizontal line SL.sub.i, the lower the impedance between the horizontal line SL.sub.i and the ground with the integrated amount of the light. Thus, even one horizontal retracing period of about 60 .mu.sec. can not be neglected. Therefore, there has been worked in the conventional example a system wherein the switching transistor Q.sub.T shown in FIG. 2A is inserted, the parasitic capacitor (C.sub.SL +C.sub.L ') is charged in precharging the signal reading line, then the address gate pulses .phi..sub.Gj are immediately impressed, the light informations of the respective picture elements C.sub.1j, C.sub.2j, C.sub.3j, . . . C.sub.nj are accumulated as discharged amounts of the parasitic capacitors (C.sub.SL +C.sub.SL ') of the respective signal reading lines SL.sub.1, SL.sub.2, SL.sub.3, . . SL.sub.n, then the switching transistor Q.sub.T is immediately switched off and the informations of the respective picture elements are accumulated only in the capacitor C.sub.SL ' and are taken out in the output line irrespectively of the discharged amount of the capacitor C.sub.SL by the horizontal shift pulses .phi..sub.S1, .phi..sub.S2, . . . , .phi..sub.Sn FIG. 2B shows the operation waveforms of the conventional system over two horizontal periods.
At the time t.sub.1, the transfer gate pulses .phi..sub.T are impressed and the switching transistors Q.sub.T on the respective signal reading lines are simultaneously made conductive and, at the time t.sub.2, the precharging pulses .phi..sub.P are impressed, the precharging transistors on the respective signal reading lines are simultaneously made conductive and the capacitors (C.sub.SL +C.sub.SL ') of the respective signal reading lines are charged to the predetermined precharged voltage level. Then, at the time t.sub.3, the respective SIT's of the picture elements C.sub.1j, C.sub.2j, C.sub.3j, . . . C.sub.nj are simultaneously made conductive by the address gate pulses .phi..sub.Gj, the light informations accumulated in the gates of the respective SIT's are moved onto the respective signal reading lines SL.sub.1, SL.sub.2, . . . SL.sub.n as discharged amounts of the parasitic capacitors (S.sub.SL +C.sub.SL ') and then immediately, at the time t.sub.4, the switching transistor Q.sub.T is switched off and the capacitors C.sub.SL and C.sub.SL ' are separated from each other. Then, at the times t.sub.5, t.sub.6, t.sub.7, . . . , the horizontal shift pulses .phi..sub.S1, .phi..sub.S2, .phi..sub.S3, . . . , .phi..sub.Sn are added in turn to the gates of the switching transistors Q.sub.S on the respective signal reading lines and the respective capacitors C.sub.SL ' are recharged with the discharged amounts from the video voltage V.sub.DD so that the output voltage V.sub.out can be obtained at each end of the load resistance R.sub.L. In the same manner, in the next horizontal period, the next picture elements C.sub.1j+1, C.sub.2j+1, C.sub.3j+1, . . . C.sub.nj+1 are read out.
The actually used numerical time values shall be described. In the case of TV signals, the number of picture elements must be about 500.times.500 and therefore one horizontal reading period will be about 65 .mu.sec. In this case, the reading time constant of one picture element will be easily realized to be several 10 n sec. in the area sensor of the SIT and the pulse width of the transfer gate pulse .phi..sub.T which is about the sum of the pulse width of the precharging pulse .phi..sub.P and the pulse width of the address gate pulse .phi..sub.Gj will be sufficient with less than 5 .mu.sec. Therefore, if the reading system by the system shown in FIGS. 2A and 2B is used, the picture image informations of about 500.times.500 elements will be easily read out by using TV signals. In the case of this conventional system, the time constant in the case that they are read out by the pulses of the horizontal shift pulses .phi..sub.S will be the time constant of charging the capacitor C.sub.SL ' as described above, the capacitor (C.sub.SL +C.sub.SL ') will not be charged, therefore the speed will be easily made higher and the time constant of about several 10 n sec. will be easily realized. In order to make the velocity higher, the parasitic capacitance and effective resistance of the video output line 51 are reduced.
However, in the formation of the two-dimensional solid-state image pickup device shown in FIGS. 2A and 2B, the source zones of the SIT's forming the respective picture elements C.sub.ij are electrically common over all the picture elements, the drain zones of the respective picture elements C.sub.il, C.sub.i2, . . . , C.sub.im arranged on the same signal reading line SL.sub.i are commonly connected to the signal reading line SL.sub.i and therefore normally off SIT's must be used for the SIT's forming the respective picture elements C.sub.ij. Further, for the normally off SIT's, devices in which the leakage current between the drain and source in the dark current state is so little as to be less than 10.sup.-13 (A) at the time of zero gate bias with a cell size of dimensions, for example, of 50.mu..times.50.mu. must be uniformly arranged. The photosensitivity of such normally off SIT is close to the photosensitivity of a bipolar transistor, is of an optical gain of about 10.sup.2 to 10.sup.3 and is not so high. In the formation in FIGS. 2A and 2B, m picture elements are arranged on one signal reading line SL.sub.i and ideally the current corresponding to the light intensity may flow through only the picture element selected by the gate pulses .phi..sub.Gj but, in fact even in the (m-1) picture elements not selected, the leakage current will flow between the drain and source when not selected. In order to control this current, the SIT must be normally off. Now, in the case of the worst condition that such strong light as of a saturated exposure amount enters all the picture elements not selected, when the leak current between the drain and source flowing through the respective picture elements gate-biased by the light is represented by I', this current will flow through the capacitor (C.sub.SL +C.sub.SL ') for the time t.sub.pt after the precharged pulses .phi..sub.P are cut until the transfer gate pulses .phi..sub.T are cut, and the total amount Q' of the electric charge flowing out of the capacitor (C.sub.SL +C.sub.SL ') will be approximately EQU Q'=(m=1)I't.sub.pt ( 7).
The potential variation V' at both ends of the capacitor (C.sub.SL +C.sub.SL ') by this electric charge will be ##EQU4## As the maximum value of the potential variation at both ends of the capacitor (C.sub.SL +C.sub.SL ') is substantially the video voltage level V.sub.DD, the ratio of the potential variation V' to the video voltage level V.sub.DD will be ##EQU5## If V.sub.DD =1 V, C.sub.SL +C.sub.SL '=1pF and t.sub.pt =1 .mu.sec. as the most practical numerical values, the value of I' required to control V'/V.sub.DD to be less than 0.1% will be required to be so small that,
when m=500, I'&lt;2.times.10.sup.-12 (A) and PA1 when m=1000, I'&lt;1.times.10.sup.-12 (A).
The reason why such small leaking currrent is required is that the drains and sources of the SIT's forming the picture elements C.sub.i1, C.sub.i2, C.sub.im on the same signal reading line are made respectively electrically common. In the case of the conventional example, the condition for controlling the amount of discharge throught the unselected picture elements during the time t.sub.pt after the precharging pulses .phi..sub.P are cut until the transfer gate pulses .phi..sub.T are cut is considerably severe as described above.
Therefore, it has been found that, if the source regions of the respective SIT's forming the picture elements C.sub.i1, C.sub.i2, C.sub.i3, . . . , C.sub.im on the same signal reading lines are connected to the respectively separate source lines BL.sub.1, BL.sub.2, BL.sub.3, . . . , BL.sub.m which are made to have a constant capacitor C.sub.BL in the unselected state to control the discharge through the SIT's and the selected source line is earthed only when selected to discharge the precharged level of the capacitor (C.sub.SL +C.sub.SL ') through the SIT, the crosstalk between both picture elements will be solved.
Generally, the photosensitivity of an SIT image sensor of a gate accumulating system having as a fundamental formation of one picture element the formation consisting of an SIT and gate capacitor C.sub.G corresponds just to the photosensitivity of the SIT when the gate is opened. When the gate is opened, the optical gain of the SIT will greatly depend on the gate structure of the SIT. If the height of a potential barrier within an n.sup.- channel as seen from a source n.sup.+ region is represented by V.sub.biG*S and the diffused potential between a p.sup.+ gate and n.sup.+ source region is represented by V.sub.biGS, the maximum value of the direct current optical gain G.sub.max will be approximately represented by ##EQU6## where n.sub.S, P.sub.G, V.sub.n, V.sub.P, q, k and T represent respectively an electron density of the source region, positive hole density of the gate region, average velocity of electrons at the intrinsic gate point, diffusing velocity of the positive holes of the gate into the source region, unit electric charge, Boltzmann's constant and absolute temperature. There is a feature that the weaker the light intensity, the larger the optical gain. The formula (10) is of a value of the light intensity at the minimum. The term of exp q/kT (V.sub.biGS -V.sub.biG*S) in the formula (10) relates to the difference between the height of the potential barrier of the positive holes accumulated in the gate and the height of the potential barrier of electrons at the source and is about 10.sup.7 to 10.sup.8. In the case of a device having such high V.sub.biG*S as V.sub.biGs .apprxeq.V.sub.biG*S among the normally off SIT's, the optical gain will be about 10.sup.2 to 10.sup.3. For the normally off SIT forming the picture element of the two-dimensional solid-state image pickup shown in FIGS. 2A and 2B, the leakage current in the dark current state between the drain and source must be made less than 10.sup.-13 a device of a cell size, for example, of 50.mu..times.50.mu.. Thus, the devcie in which the leakage current between the drain and source is little must be designed so that the height V.sub.biG*S of the potential barrier within the channel may be necessarily high and does not well utilize the intrinsic high photosensitivity of the SIT. The great reason for this is the signal crosstalk between the picture elements when arranged in the form of a matrix as described above. In the conventional example in FIGS. 2A and 2B, the drain and source regions of the SIT's forming the respective picture elements on the same signal reading lines SL.sub.i (i=1.about.n) are respectively electrically common. The photosensitivity of the SIT forming the picture element in the case of the conventional example in FIGS. 2A and 2B is about 10.sup.2 to 10.sup.3 but, as the same n.sup.+ substrate or n.sup.+ buried layer can be utilized, the formation of the two-dimensional arrangement is simple and the reading method is also simple.
In the conventional example explained with reference to FIGS. 2A and 2B, in the SIT's forming the picture elements, all the picture elements are electrically common and, in the SIT's arranged on the same signal reading lines, the source regions and drain regions are common. Therefore, when the light enters the picture element in which the gate is not selected and the impedance between the source and drain of the SIT reduces, the current flowing as a discharged current from the capacitor (C.sub.SL +C.sub.SL ') will be likely to be detected as a false signal. In order to control such false signal to be below 0.1% of such saturated output as, for example, V.sub.DD =1 V, the current flowing through the picture element when the gate is biased with the light when not selected must be less than 2.times.10.sup.-12 (A) in the matrix of 500.times.500 picture elements and must be considerably characteristic of being normally off. Further, as explained with the formula (10), as the value of the height V.sub.biG*S of the potential barrier within the channel becomes closer to the potential difference V.sub.biGS between the gate and source, the photosensitivity of such SIT will not become so high. In the case of the conventional example, in case there is a faulty picture element (short-circuited) in the matrix, even the other picture elements connected to the same signal reading line will be considered to be short-circuited and the influence on the adjacent picture elements will be large.